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vishay siliconix dg4051a, dg4052a, dg4053a document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 1 8-channel, dual 4-channel, triple 2-channel (triple spdt) multiplexers features ? + 2.7 v to + 12 v single supply operation 2.5 v to 5 v dual supply operation ? fully specified at + 3 v, + 5 v, 5 v ? 100 ? maximum on-resistance ? low voltage, 2.5 v cmos/ttl compatible ? low charge injection (< 0.5 pc typ.) ? high - 3 db bandwidth: 330 mhz to 700 mhz ? low switch capacitance (c s(off) 3 pf typ.) ? excellent isolation and crosstalk performance (typ. 47 db at 100 mhz) ? 16 pin soic, tssop and miniqfn package (1.8 mm x 2.6 mm) ? fully specified from - 40 c to + 85 c and - 40 c to + 125 c ? compliant to rohs directive 2002/95/ec applications ? instruments ? healthcare and medical equipments ? touch panel ? automated test equipment ? automation and control ? high precision data acquisition ? communication system description the dg4051a, dg4052a and dg 4053a are high precision cmos analog multiplexers. the dg4051a is an 8-channel multiplexer, the dg4052a is a dual 4-channel multiplexer and the dg4053a is a triple 2-channel multiplexer or triple spdt. designed to operate from a + 2.7 v to + 12 v single supply or from a 2.5 v to 5 v dual supplies, the dg4051a, dg4052a and dg4053a are fully specified at + 3 v, + 5 v and 5 v. all control logic inputs have guaranteed 2.0 v logic high limit when operating from + 5 v or 5 v supplies and 1.4 v when operating from a + 3 v supply. channel leakage is typically in the range of 10 pa, and switch charge injection is less than 0.5 pc. coupled with very low switch capacitance, thes e devices are ideal for high precision signal switching and multiplexing. all switches conduct equally well in both directions, offering rail to rail analog signal switching and can be used both as multiplexers as well as de-multiplexers. the dg4051a, dg4052a and dg4053a operating temperature is specified from - 40 c to + 125 c and are available in 16 pin tssop and the ultra compact 1.8 mm x 2.6 mm miniqfn16 packages. functional block diagram and pin configuration e n able = lo, all s w itches are controlled b y addr pins. e n able = hi, all s w itches are off. x0 a x3 11 12 13 14 x2 c b x1 v cc 9 10 16 15 x x7 x5 v ee x4 x6 e n able g n d 3 4 5 6 1 2 7 8 top v ie w dg4051a tssop16 top v ie w dg4052a tssop16 y y3 y1 x y0 y2 x0 a x3 11 12 13 14 x2 b x1 v cc 9 10 16 15 v ee e n able g n d 3 4 5 6 1 2 7 8 logic logic e n able dg4053a tssop16 c top v ie w y z0 y1 x y0 z1 x0 a 11 12 13 14 z b x1 v cc 9 10 16 15 v ee e n able g n d 3 4 5 6 1 2 7 8 rohs compliant
www.vishay.com 2 document number: 69828 s10-1383-rev. e, 21-jun-10 vishay siliconix dg4051a, dg4052a, dg4053a functional block diagram and pin configuration notes: a. - 40 c to 85 c datasheet limits apply. pin 1 de v ice marking: exx for dg4051a (miniqf n 16) fxx for dg4052a gxx for dg4053a xx = date/lot tracea b ility code exx x x7 x5 x0 a x3 1 2 3 4 7 8 9 10 11 12 5 8 7 6 13 14 x4 16 v ee x2 c x6 e n able b x1 g n d v cc top v ie w dg4051a mqf n -16 top v ie w dg4052a mqf n -16 logic y y3 y1 x x3 x0 1 2 3 4 8 9 10 11 12 5 8 6 13 14 y0 16 v ee x2 b y2 e n able a x1 g n d logic 15 15 7 v cc z1 z z0 1 2 3 4 7 8 9 10 11 12 5 8 7 6 13 14 15 16 y y1 y0 g n d top v ie w dg4053a mqf n -16 v cc e n able v ee a b c x1 x x0 truth table enable input select inputs on switches c b a dg4051a dg4052a dg4053a h x x x all switches open all swit ches open all switches open l l l l x to x0 x to x0, y to y0 x to x0, y to y0, z to z0 l l l h x to x1 x to x1, y to y1 x to x1, y to y0, z to z0 l l h l x to x2 x to x2, y to y2 x to x0, y to y1, z to z0 l l h h x to x3 x to x3, y to y3 x to x1, y to y1, z to z0 l h l l x to x4 x to x0, y to y0 x to x0, y to y0, z to z1 l h l h x to x5 x to x1, y to y1 x to x1, y to y0, z to z1 l h h l x to x6 x to x2, y to y2 x to x0, y to y1, z to z1 l h h h x to x7 x to x3, y to y3 x to x1, y to y1, z to z1 ordering information temp range package part number dg4051a, dg4052a, dg4053a - 40 c to 125 c a 16-pin tssop dg4051aeq-t1-e3 dg4052aeq-t1-e3 dg4053aeq-t1-e3 16-pin miniqfn DG4051AEN-T1-E4 dg4052aen-t1-e4 dg4053aen-t1-e4
document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 3 vishay siliconix dg4051a, dg4052a, dg4053a notes: a. signals on sx, dx, or inx exceeding v+ or v- will be clam ped by internal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 5.6 mw/c above 70 c. d. derate 6.6 mw/c above 70 c. e. manual soldering with iron is not recommended for leadless co mponents. the miniqfn-16 is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper l ip cannot be guaranteed and is not required to ensure adequa te bottom side solder interconnection. absolute maximum ratings t a = 25 c, unless otherwise noted parameter limit unit v+ to v- 14 v gnd to v- 7 digital inputs a , v s , v d (v-) - 0.3 to (v+) + 0.3 or 30 ma, whichever occurs first continuous current (any terminal) 30 ma peak current, s or d (pulsed 1 ms, 10 % duty cycle) 100 storage temperature - 65 to 150 c power dissipation b 16-pin tssop c 450 mw 16-pin miniqfn d, e 525 thermal resistance b 16-pin tssop 178 c/w 16-pin miniqfn e 152 specifications for dual supplies parameter symbol test conditions unless otherwise specified v cc = + 5 v, v ee = - 5 v v in(a, b, c and enable) = 2.0 v, 0.8 v a temp. b typ. c - 40 c to 125 c - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 55- 55v on-resistance r on i s = 1 ma, v d = - 3 v, 0 v, + 3 v room full 66 100 125 100 118 ? on-resistance match ? r on i s = 1 ma, v d = 3 v room full 36 10 6 8 on-resistance flatness r flatness i s = 1 ma, v d = - 3 v, 0 v, + 3 v room full 12 16 20 16 18 switch off leakage current i s(off) v+ = 5.5 v, v- = - 5.5 v, v d = 4.5 v, v s = 4.5 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 na i d(off) room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 channel on leakage current i d(on) v+ = 5.5 v, v- = - 5.5 v, v s = v d = 4.5 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 digital control input current, v in low i il v in(a, b, c and enable) under test = 0.8 v full0.01- 11- 11 a input current, v in high i ih v in(a, b, c and enable) under test = 2.0 v full0.01- 11- 11 input capacitance e c in f = 1 mhz room 3.4 pf dynamic characteristics off isolation oirr r l = 50 ? , c l = 1 pf f = 10 mhz room 67 db f = 100 mhz room 46 channel-to-channel crosstalk x ta l k f = 10 mhz room 67 f = 100 mhz room 47 bandwith, 3 db bw r l = 50 ? dg4051a room 330 mhz dg4052a room 450 dg4053a room 730
www.vishay.com 4 document number: 69828 s10-1383-rev. e, 21-jun-10 vishay siliconix dg4051a, dg4052a, dg4053a dynamic characteristics transition time t trans r l = 300 ? , c l = 35 pf see figure 1, 2, 3 room full 36 110 127 110 117 ns enable turn-on time t on room full 31 108 119 108 114 enable turn-off time t off room full 29 92 103 92 98 break-before-make time delay t d room full 11 charge injection e q v g = 0 v, r g = 0 ? , c l = 1 nf room 0.25 pc off isolation e oirr r l = 50 ? , c l = 1 pf f = 100 khz room < - 90 db channel-to-channel crosstalk e x ta l k room < - 90 source off capacitance e c s(off) f = 1 mhz dg4051a room 3 pf dg4052a room 3 dg4053a room 3 drain off capacitance e c d(off) f = 1 mhz dg4051a room 12 dg4052a room 7 dg4053a room 4 channel on capacitance e c d(on) f = 1 mhz dg4051a room 17 dg4052a room 13 dg4053a room 11 total harmonic distortion e thd signal = 5 v rms , 20 hz to 20 khz, r l = 600 ? room 0.28 % power supplies power supply current i+ v cc = + 5 v, v ee = - 5 v v in(a, b, c and enable) = 0 or 5 v room full 0.05 1 10 1 10 a negative supply current i- room full - 0.05 - 1 - 10 - 1 - 10 ground current i gnd room full - 0.05 - 1 - 10 - 1 - 10 specifications for dual supplies parameter symbol test conditions unless otherwise specified v cc = + 5 v, v ee = - 5 v v in(a, b, c and enable) = 2.0 v, 0.8 v a temp. b typ. c - 40 c to 125 c - 40 c to 85 c unit min. d max. d min. d max. d
document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 5 vishay siliconix dg4051a, dg4052a, dg4053a specifications for unipolar supplies parameter symbol test conditions unless otherwise specified v cc = + 5 v, v ee = 0 v v in(a, b, c and enable) = 2.0 v, 0.8 v a temp. b typ. c - 40 c to 125 c - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0505v on-resistance r on i s = 1 ma, v d = 0 v, + 3.5 v room full 107 165 205 165 194 ? on-resistance match ? r on i s = 1 ma, v d = + 3.5 v room full 3.2 8 13 8 11 on-resistance flatness r flatness i s = 1 ma, v d = 0 v, + 3 v room full 19 26 30 26 28 switch off leakage current i s(off) v+ = + 5.5 v, v- = 0 v v d = 1 v/4.5 v, v s = 4.5 v/1 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 na i d(off) room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 channel on leakage current i d(on) v+ = + 5.5 v, v- = 0 v v d = v s = 1 v/4.5 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 digital control input current, v in low i l v in(a, b, c and enable) under test = 0.8 v full0.01- 11- 11 a input current, v in high i h v in(a, b, c and enable) under test = 2.0 v full0.01- 11- 11 dynamic characteristics transition time t trans r l = 300 ? , c l = 35 pf see figure 1, 2, 3 room full 38 121 143 121 134 ns enable turn-on time t on room full 38 110 126 110 119 enable turn-off time t off room full 38 103 118 103 111 break-before-make time delay t d room full 11 charge injection e q v g = 0 v, r g = 0 ? , c l = 1 nf full 0.5 pc off isolation e oirr r l = 50 ? , c l = 1 pf f = 100 khz room < - 90 db channel-to-channel crosstalk e x ta l k room < - 90 source off capacitance e c s(off) f = 1 mhz dg4051a room 3 pf dg4052a room 3 dg4053a room 4 drain off capacitance e c d(off) f = 1 mhz dg4051a room 13 dg4052a room 8 dg4053a room 5 channel on capacitance e c d(on) f = 1 mhz dg4051a room 18 dg4052a room 14 dg4053a room 11 power supplies power supply current i+ v in(a, b, c and enable) = 0 v or 5 v room full 0.05 1 10 1 10 a negative supply current i- room full - 0.05 - 1 - 10 - 1 - 10 ground current i gnd room full - 0.05 - 1 - 10 - 1 - 10
www.vishay.com 6 document number: 69828 s10-1383-rev. e, 21-jun-10 vishay siliconix dg4051a, dg4052a, dg4053a notes: a. v in = input voltage to perform proper function. b. room = 25 c, full = as determin ed by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications for unipolar supplies parameter symbol test conditions unless otherwise specified v cc = + 3 v, v ee = 0 v v in(a, b, c and enable) = 1.4 v, 0.6 v a temp. b typ. c - 40 c to 125 c - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0303v on-resistance r on i s = 1 ma, v d = 1.5 v room full 175 265 310 265 298 ? switch off leakage current i s(off) v+ = + 3.3 v, v- = 0 v v d = 0.3 v/3.0 v, v s = 3.0 v/0.3 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 na i d(off) room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 channel on leakage current i d(on) v+ = + 3.3 v, v- = 0 v v d = v s = 0.3 v/3.0 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 digital control input current, v in low i l v in(a, b, c and enable) under test = 0.6 v full 0.01 - 1 1 - 1 1 a input current, v in high i h v in(a, b, c and enable) under test = 1.4 v full 0.01 - 1 1 - 1 1 dynamic characteristics transition time t trans r l = 300 ? , c l = 35 pf see figure 1, 2, 3 room full 81 172 218 172 194 ns enable turn-on time t on room full 71 151 183 151 167 enable turn-off time t off room full 69 138 161 138 151 break-before-make time delay t d room full 11 charge injection e q v g = 0 v, r g = 0 ? , c l = 1 nf room 0.5 pc off isolation e oirr r l = 50 ? , c l = 1 pf f = 100 khz room < - 90 db channel-to-channel crosstalk e x ta l k room < - 90 source off capacitance e c s(off) f = 1 mhz dg4051a room 4 pf dg4052a room 3 dg4053a room 4 drain off capacitance e c d(off) f = 1 mhz dg4051a room 14 dg4052a room 8 dg4053a room 5 channel on capacitance e c d(on) f = 1 mhz dg4051a room 19 dg4052a room 14 dg4053a room 11 power supplies power supply current i+ v in(a, b, c and enable) = 0 v or 3 v room full 0.05 1 10 1 10 a negative supply current i- room full - 0.05 - 1 - 10 - 1 - 10 ground current i gnd room full - 0.05 - 1 - 10 - 1 - 10
document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 7 vishay siliconix dg4051a, dg4052a, dg4053a typical characteristics 25 c, unless otherwise noted on-resistance vs. v d and single supply voltage on-resistance vs. analog voltage and temperature at v cc = + 3 v, v ee = 0 v on-resistance vs. analog voltage and temperature at v cc = + 5 v, v ee = - 5 v v d - analog voltage (v) r on - on-resistance ( ? ) 0 50 100 150 200 250 300 350 400 450 500 0 2 4 6 8 10 12 14 v cc = 3.0 v t = 25 c i s = 1 ma v cc = 2.7 v v cc = 5.0 v v cc = 12 v 0 50 100 150 200 250 300 350 400 450 500 0 0.5 1 1.5 2 2.5 3 v d - analog voltage (v) r on - on-resistance ( ? ) + 85 c + 25 c - 40 c v cc = 3.0 v, v ee = 0 v i s = 1 ma + 125 c 0 25 50 75 100 125 150 175 200 225 250 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 v d - analog voltage (v) r on - on-resistance ( ? ) + 125 c + 85 c + 25 c - 40 c v cc = 5.0 v, v ee = - 5.0 v i s = 1 ma on-resistance vs. v d and dual supply voltage on-resistance vs. analog voltage and temperature at v cc = + 5 v, v ee = 0 v supply current vs. input switching frequency 0 50 100 150 200 250 300 - 8- 6- 4- 202468 v d - analog voltage (v) r on - on-resistance ( ? ) t = 25 c i s = 1 ma v cc = + 2.7 v v ee = - 2.7 v v cc = + 5.0 v v ee = - 5.0 v v cc = + 6.2 v v ee = - 6.2 v 0 50 100 150 200 250 300 350 400 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v d - analog voltage (v) r on - on-resistance ( ? ) + 125 c + 85 c + 25 c - 40 c v cc = 5.0 v, v ee = 0 v i s = 1 ma input switching frequency (hz) supply current (a) 10 100 1k 10k 100k 1m 10m i gnd i ee 10 ma 1 ma 100 a 10 a 1 a 100 na 10 na 1 na 100 pa i cc v cc = + 5 v v ee = - 5 v
www.vishay.com 8 document number: 69828 s10-1383-rev. e, 21-jun-10 vishay siliconix dg4051a, dg4052a, dg4053a typical characteristics 25 c, unless otherwise noted leakage current vs. temperature switching time vs. temperature dg4052a insertion loss, off-isolation, crosstalk vs. frequency at 5 v supply 1 10 100 1000 10 000 100 000 - 60 - 40 - 20 0 20 40 60 80 100 120 140 temperature (c) leakage current (pa) i d(on) i d(off) i s(off) v cc = + 5.5 v v ee = - 5.5 v 0 20 40 60 80 100 120 - 60 - 40 - 20 0 20 40 60 80 100 120 140 temperature (c) t on(en) , t off(en) - switching time (ns) t on v cc = + 3.0 v, v ee = 0 v t on v cc = + 5.0 v, v ee = 0 v t off /t on v cc = + 5.0 v, v ee = - 5.0 v t off v cc = + 5.0 v, v ee = 0 v t off v cc = + 3.0 v, v ee = 0 v - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 frequency (hz) loss, oirr, x talk (db) 100k 1m 10m 100m 1g oirr loss x talk v cc = + 5.0 v v ee = - 5.0v r l = 50 ? 1 10 100 1000 10 000 100 000 - 60 - 40 - 20 0 20 40 60 80 100 120 140 temperature (c) leakage current (pa) i d(on) i d(off) i s(off) v cc = + 13.2 v v ee = 0 v - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 frequency (hz) loss, oirr, x talk (db) 100k 1m 10m 100m 1g oirr loss x talk v cc = + 5.0 v v ee = - 5.0 v r l = 50 ? - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 frequency (hz) loss, oirr, x talk (db) 100k 1m 10m 100m 1g v cc = + 5.0 v v ee = - 5.0 v r l = 50 ?? oirr loss x talk
vishay siliconix dg4051a, dg4052a, dg4053a document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 9 typical characteristics 25 c, unless otherwise noted switching threshold vs. v cc supply voltage dg4052a charge injection vs. analog voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 02468101214 v cc supply voltage (v) v t - switching threshold (v) - 40 c to + 125 c - 2.00 - 1.75 - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 - 5- 4- 3- 2- 1012345 v s - analog voltage (v) q inj - charge injection (pc) v cc = + 5.0 v v ee = - 5.0 v v cc = + 3.0 v v ee = 0 v v cc = + 5.0 v v ee = 0 v dg4051a charge injection vs. analog voltage dg4053a charge injection vs. analog voltage - 2.00 - 1.75 - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 v s - analog voltage (v) q inj - charge injection (pc) v cc = + 5.0 v v ee = - 5.0 v v cc = + 3.0 v v ee = 0 v v cc = + 5.0 v v ee = 0 v - 2.00 - 1.75 - 1.50 - 1.25 - 1.00 - 0.75 - 0.50 - 0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 v s - analog voltage (v) q inj - charge injection (pc) v cc = + 5.0 v v ee = - 5.0 v v cc = + 3.0 v v ee = 0 v v cc = + 5.0 v v ee = 0 v
www.vishay.com 10 document number: 69828 s10-1383-rev. e, 21-jun-10 vishay siliconix dg4051a, dg4052a, dg4053a test circuits figure 1. transition time a b c e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x x0 x7 x1 - x6 dg4051a v x0 v x7 a b e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x or y x0 or y0 x3 or y3 x1 - x2 or y1 - y2 dg4052a v x0 or v y0 v x3 or v y3 a or b or c e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x or y or z x0 or y0 or z0 x1 or y1 or z1 dg4053a v x0 or v y0 or v z0 v x1 or v y1 or v z1 0 v v cc 50 % 90 % t tra n s x0 or y0 or z0 o n x7 o n (dg4051a) or x3 or y3 o n (dg4052a) or x1 or y1 or z1 o n (dg4053a) v o v a,b,c v x0 or v y0 or v z0 v x1 or v y1 or v z1 v x3 or v y3 v x7 t tra n s 90 %
vishay siliconix dg4051a, dg4052a, dg4053a document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 11 test circuits figure 2. enable switching time a b c e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x x0 x1 - x7 dg4051a a b e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x or y x0 or y0 x1 - x3 or y1 - y3 dg4052a a or b or c e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x or y or z x0 or y0 or z0 x1 or y1 or z1 dg4053a 0 v v cc 50 % 90 % t off x0 or y0 or z0 o n x7 o n (dg4051a) or x3 or y3 o n (dg4052a) or x1 or y1 or z1 o n (dg4053a) v o v enable v x0 or v y0 or v z0 v cc 0 v v cc v cc t o n 90 %
www.vishay.com 12 document number: 69828 s10-1383-rev. e, 21-jun-10 vishay siliconix dg4051a, dg4052a, dg4053a test circuits figure 3. break-before-make a b c e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x x0 - x7 dg4051a a b e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x or y x0 - x3 or y0- y3 dg4052a a or b or c e n able g n d v cc v ee v ee v cc v o 50 300 35 pf x or y or z x0, x1 or y0, y1 or z0, z1 dg4053a 0 v v cc 50 % 8 0 % t d v o v a,b,c v x0 or v y0 or v z0 v cc v cc v cc 0 v figure 4. charge injection a b c e n able g n d v cc v ee v ee v cc v o 1 nf x or y or z xx or yx or zx 0 v v cc v o v enable r g channel select v g o n off off v o t r < 5 ns t f < 5 ns
vishay siliconix dg4051a, dg4052a, dg4053a document number: 69828 s10-1383-rev. e, 21-jun-10 www.vishay.com 13 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69828 . figure 5. insertion loss figure 7. crosstalk a b c e n able g n d v cc v ee v ee v cc v out x or y or z x0 or y0 or z0 v g r g = 50 50 v i n n et w ork analyzer insertion loss = 20 log v out v i n a b c e n able g n d v cc v ee v ee v cc v out x or y or z x0 or y0 or z0 v g r g = 50 50 v i n n et w ork analyzer crosstalk = 20 log v out v i n 50 xx or yx or zx figure 6. off isolation figure 8. source, drain capacitance a b c e n able g n d v cc v ee v ee v cc v out x or y or z x0 or y0 or z0 v g r g = 50 50 v i n n et w ork analyzer off isolation = 20 log v out v i n v cc a b c e n able g n d v cc v ee v ee v cc x or y or z x0 or y0 or z0 | to | xx or yx or zx impedance analyzer channel select
vishay siliconix package information document number: 74323 14-aug-06 www.vishay.com 1 mini qfn-16l dim millimeters inches min. nam max. min. nam max. a 0.70 0.75 0.80 0.0275 0.0295 0.0315 a1 0 - 0.05 0 - 0.002 b 0.15 0.20 0.25 0.0059 0.0078 0.0098 c 0.15 0.20 0.25 0.0059 0.0078 0.0098 d 2.60 bsc 0.1023 bsc e 1.80 bsc 0.0708 bsc e 0.40 bsc 0.0157 bsc l 0.35 0.40 0.45 0.0137 0.0157 0.0177 l1 0.45 0.50 0.55 0.0177 0.0196 0.0216 ecn t-06380-rev. a, 14-aug-06 dwg: 5954 back side v ie w d e (2) (1) (16) (15) (14) (13) a c b e l a1 (4) (3) (5) (6) (7) ( 8 ) (9) (12) (11) (10) (10) (9) (12) (11) (3) (2) (1) (4) (16) (15) (14) (13) (5) (6) (7) ( 8 ) l1
vishay siliconix package information document number: 74417 23-oct-06 www.vishay.com 1 symbols dimensions in millimeters min nom max a - 1.10 1.20 a1 0.05 0.10 0.15 a2 - 1.00 1.05 b 0.22 0.28 0.38 c - 0.127 - d 4.90 5.00 5.10 e 6.10 6.40 6.70 e1 4.30 4.40 4.50 e-0.65- l 0.50 0.60 0.70 l1 0.90 1.00 1.10 y--0.10 1036 ecn: s-61920-rev. d, 23-oct-06 dwg: 5624 tssop: 16-lead
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